Manufacture of many electronic components, including flat panel displays, RFID tags, and various sensing applications, relies upon accurately patterning layers of electrically active materials applied to a relatively large substrate. These products are composed of several layers of different patterned materials, where it is important that the layers be in specific registration. The reasons for patterning accuracy are twofold. First of all, patterned features must be reproduced across large areas of a substrate while having precise control over their dimensions. Secondly, products built with these features typically are composed of several layers of different, but interacting patterned layers, where it is important that the layers be in specific registration or alignment.
Traditionally, the precise layer alignment required for fabrication of electronic components and devices is accomplished using conventional photolithography. An electrically active layer and a photoresist layer are deposited on a substrate, the position of an existing pattern on the substrate is detected, and an exposure mask is aligned to that existing pattern. The photoresist is exposed, developed, and the electrically active material is etched. Small variations in temperature and humidity in this precise operation may be enough to introduce alignment errors; rigid glass substrates are used with stringent environmental controls to reduce these variations. At the other extreme, conventional printing techniques such as offset lithography, flexography, and gravure printing also apply multiple layers at extremely high speeds, although at substantially lower overlay accuracy.
There is a growing interest in advancing printing technology toward fabrication of thin film electrical components (such as TFTs) on flexible or plastic substrates. These substrates would be mechanically robust, lighter weight, and eventually lead to lower cost manufacturing by enabling roll-to-roll processing. In spite of the potential advantages of flexible substrates, there are many issues affecting the performance and ability to perform alignments of transistor components across typical substrate widths up to one meter or more. In particular, for example, the overlay accuracy achievable using traditional photolithography equipment can be seriously impacted by substitution of a flexible plastic substrate for the rigid glass substrates traditionally employed. Dimensional stability, particularly as the process temperature approaches the glass transition temperature (Tg) of supports, water and solvent swelling, anisotropic distortion, and stress relaxation are all key parameters in which plastic supports are inferior to glass.
Typical fabrication involves sequential deposition and patterning steps. Three types of registration errors are common in these fabrication processes: fixed errors, scale errors, and local misalignments. The fixed error, which refers to a uniform shift of one pattern to another, is typically dominated by the details of the motion control system. Specifically, mechanical tolerances and details of the system integration ultimately dictate how accurately the substrate may be aligned to a mask, or how accurately an integrated print device may be positioned with respect to a registration mark on a moving web. In addition to fixed errors, scale errors may also be substantial. Errors in pattern scale are cumulative across the substrate and arise from support dimensional change, thermal expansion, and angular placement errors of the substrate with the patterning device. Although the motion control system impacts angular placement, pattern scale mismatch is largely driven by the characteristics of the support. Thermal expansion, expansion from humidity or solvent exposure, shrinkage from high temperature exposure, and stress relaxation (creep) during storage of the support all contribute to pattern scale errors. Further, local pattern mismatch arising from nonisotropic deformations may also occur, particularly since the conveyance process involves applying tension. A flexible support used in roll-to-roll manufacturing will typically stretch in the conveyance direction and narrow in width.
There are several approaches to address the registration problem for fabrication of electronics on flexible substrates, but at this point a leading methodology has yet to emerge. Attach/detach technology has been explored by French et al, wherein a flexible substrate is laminated to a rigid carrier and runs through a traditional photolithographic process (I. French et al., “Flexible Displays and Electronics Made in AM-LCD Facilities by the EPLaRTM Process” SID 07 Digest, pp. 1680-1683 (2007)). Unfortunately, these technologies ultimately produce a flexible electronics component only with the cost structure of current glass based processing. US Patent Publication No. 2006/0063351 by Jain describes coating the front side and back side of a substrate with one or more resist layers that may be activated simultaneously to impart distinct pattern images within each resist layer. The precoated substrate is inserted between a set of prealigned masks, or alternatively a dual wavelength maskless direct laser writing lithography system is used, to simultaneously expose the front and back sides. Active alignment systems to detect previously existing patterns and compensation schemes for deformation have also been suggested in U.S. Pat. No. 7,100,510, by Brost et al. With this approach, instead of attaining accurate pattern overlay by maintaining tight specs on support dimensional stability and strict environmental control, the motion control system performs multiple alignments per substrate to compensate for distortion. The proposed solution of Brost et al., to adapt traditional printing equipment for active alignment, may be viewed as exchanging the lens, mask, and lamp of a modem stepper with an integrated print device. It is difficult to imagine significant equipment cost difference or throughput advantage, particularly if the added task of distortion compensation is included. A fabrication cost advantage would likely come primarily from materials usage savings or removal of expensive vacuum deposition steps.
Another approach, which would potentially enable high speed processing with low capital investment, is to employ a self-aligning fabrication process. In a self-aligning process, a template for the most critical alignments in the desired structure is applied in one step to the substrate and from that point forward alignment of subsequent layers is automatic. Various methods have been described for fabricating self-aligned TFTs. Most of these methods allow self alignment of one layer to another layer, but do not significantly remove the need for very sophisticated alignment steps between several layers. For example, the gate electrode in some a-Si TFT processes is used as a “mask” to protect the channel area from doping and laser annealing of the silicon on either side of the channel region. The concept of self-aligned fabrication can be understood from U.S. Pat. No. 5,391,507 by Kwasnick et al., U.S. Pat. No. 6,338,988 byo Andry et al., and US Patent Publication No. 2004/229411 by Battersby.
One published technique offering the potential for a fully self aligned process that eliminates the need for complex registration is Self-Aligned Imprint Lithography (SAIL), as illustrated in U.S. Pat. No. 7,056,834 by Mei et al. In imprint lithography, a variable-thickness resist is prepared on the electronically active layers and a sequencing of chemical etch and materials deposition is matched to controlled erosion of the photoresist to produce TFT structures. There are difficulties with the SAIL process, however. First, robust nanoimprint technology is necessary for webs. Second, the SAIL process requires high accuracy etch depth control, which may not be consistent with a low cost process. Finally, a significant limitation of the SAIL process is that layers produced by the mask cannot be fully independent. As an example, it is particularly challenging to form openings under continuous layers with this approach, an essential element in a matrix backplane design.
There is also interest in utilizing lower cost processes for materials deposition that do not involve the expense associated with vacuum processing and subtractive patterning processes. In typical vacuum depositions, a large metal chamber and sophisticated vacuum pumping systems are required in order to provide the necessary environment. In typical subtractive patterning systems, much of the material deposited in the vacuum chamber is removed, for example in an etch step. These deposition and subtractive patterning methods have high capital costs and preclude the easy use of continuous web-based systems.
It would be desirable to combine materials deposition and patterning employing selective area deposition, or SAD. As the name implies, selective area deposition involves treating portion(s) of a substrate such that a material is deposited only in those areas that are desired, or selected. In this approach, a deposition process employing either liquid or vapor phase chemical delivery would be tailored to operate in a manner where material selectively deposits only in certain areas.
Atomic layer deposition (“ALD”) is an example of a film deposition technology that potentially can be used as a fabrication step for forming a number of types of thin-film electronic devices and components, including semiconductor devices and supporting electronic components such as resistors and capacitors, insulators, bus lines, and other conductive structures. ALD is particularly suited for forming thin layers of metal oxides in the components of electronic devices. General classes of functional materials that can be deposited with ALD include conductors, dielectrics or insulators, and semiconductors. One approach to combining patterning and depositing a semiconductor by ALD is shown in U.S. Pat. No. 7,160,819 by Conley, Jr. et al. Conley, Jr. et al. discuss materials for use in patterning Zinc Oxide on silicon wafers. No information is provided on the use of other substrates, or the results for other metal oxides. Sinha et al. (J. Vac. Sci. Technol. B 24 6 2523-2532 (2006)), have remarked that selective area ALD requires that designated areas of a surface be masked or “protected” to prevent ALD reactions in those selected areas, thus ensuring that the ALD film nucleates and grows only on the desired unmasked regions. It is also possible to have SAD processes where the selected areas of the surface area are “activated” or surface modified in such a way that the film is deposited only on the activated areas.
A number of materials have been used by researchers as director inhibitor compounds for selective area deposition. Sinha et al., referenced above, use poly(methyl methacrylate (PMMA) in their masking layer. Conley, Jr. et al. employed acetone and deionized water, along with other process contaminants as deposition inhibitor materials. The problem with these previously used director inhibitors is that they are only effective to direct selected thin materials. Additionally, in order to be useful in constructing devices, director inhibitor compounds need to be patterned. Additive methods of patterning director inhibitors, such as lithography or inkjet are limited in their resolution. Also, there remains a difficulty in aligning the different layers in a final device that cannot be resolved by selected area deposition alone.
Therefore, there is a need for a director inhibitor compound that can work with a range of thin film materials, is easily patterned, and is suited to highly accurate patterning in a simple way. The present invention facilitates highly accurate patterning in a simple way, and solves one or more of the aforesaid problems.